• A design flow for the precise identification of the worst-case voltage drop in power grid analyses 

      Karampatzakis, D. P.; Tsiampas, M. K.; Evmorfopoulos, N. E.; Stamoulis, G. I. (2008)
      Modern IC designs contain hundreds of millions of transistors and new implementations of multi core chips take place in commercial products. Identifying worst-case voltage drop conditions in every hierarchical module ...
    • Juxtaposing Vivado Design Flows in Batch Mode 

      Dadaliaris A., Tragoudaras A., Kranas G., Dossis M., Dimitriou G. (2021)
      Re-configurable hardware devices are at the forefront of technological advancement and academic research, with their most prominent delegate being Field Programmable Gate Arrays (FPGAs). A typical FPGA design cycle may ...
    • A Novel Genetic Algorithm for I/O Pad Planning Retaining Former Cell Positions 

      Kranas G.K., Kouskouras T.G., Dimitriadis V., Dossis M., Oikonomou P., Dadaliaris A.N. (2020)
      In a typical integrated circuit (IC) design flow, each step is executed sequentially, and valuable feedback is provided that can be utilized if we are forced to backtrack as a means to resolve problems or satisfy design ...
    • Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm 

      Toufexis, F.; Papanikolaou, A.; Soudris, D.; Stamoulis, G.; Bantas, S. (2011)
      In this work, the impact of across-chip temperature and power supply voltage variations, on performance predictions in 3D ICs, is investigated. To make this possible, a novel design flow is proposed to perform design ...
    • R-Abax: A radiation hardening legalisation algorithm satisfying TMR spacing constraints 

      Georgakidis C., Sotiriou C., Sketopoulos N., Krstic M., Schrape O., Breitenreiter A. (2020)
      Faults caused by ionising radiation have become a significant reliability issue in modern ICs. However, the Radiation Hardening (RADHARD) design flow differs from the standard design flow. Thus, there is not sufficient ...
    • Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL 

      Georgakidis C., Sotiriou C. (2020)
      Reduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening ...
    • Scavenging PyPi for VLSI Packages 

      Kranas G.K., Dadaliaris A.N., Oikonomou P., Dossis M. (2022)
      Application Specific Integrated Circuits and Field Programmable Gate Arrays as well as their respective design flows have been the focus of many studies. As such the use of EDA tools becomes a necessity while researchers ...
    • Variations on a Connectivity-based Legalizer for Standard Cell Design 

      Dadaliaris A.N., Kranas G.K., Oikonomou P., Dossis M. (2021)
      Legalization is considered the most significant step in a placement correlated standard cell design flow as moving cells towards legal positions to avoid overlap among them may escalate the overall wire length. Monolithic ...